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UCLA Adaptive Systems Laboratory

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AUB 2001
Department of Electrical Engineering
American University of Beirut, Lebanon

Signal Processing Issues in CDMA Wireless Location

June 25, 2001

Wireless location finding has emerged as an essential public safety feature of future cellular systems. This has been in response to an order issued by the federal communications commission (FCC), which mandates all wireless service providers to provide public safety answering points with information to locate an emergency 911 caller with certain accuracy. Wireless location also has many other potential applications in areas such as location sensitive billing, fraud protection, mobile yellow pages, fleet management, and person/asset tracking.

Wireless location requires accurate estimates of the time and/or amplitude of arrival of the mobile station (MS) signal when received at various base stations (BSs). Obtaining such estimates is usually difficult due to the low signal to noise ratios, fast channel fading, and multipath propagation conditions encountered in wireless propagation environments.

This work develops estimation algorithms for the time and amplitude of arrival of a CDMA signal transmitted over a fading multipath channel, which are robust to high interference levels, fast fading, and overlapping multipath propagation. A maximum likelihood estimation algorithm for the time and amplitude of arrival of a signal over a single path fading channel is developed to enhance performance in fast channel fading and low signal-to-noise ratio conditions. This estimation algorithm is extended to the multipath case to arrive at a block least-squares multipath resolving algorithm. A technique for detecting overlapping multipath components is then developed and optimized. This detection technique is used as part of a successive projections adaptive algorithm to develop more accurate alternative to the least-squares method. The dissertation also proposes an advanced location system for public safety applications and discusses efficient hardware architectures for implementing the proposed algorithms.